PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Chakrabarty, Krishnendu"

Author of the publication

copydeleteadd this publication to your clipboard
Dynamic I/O power management for hard real-time systems.

, , and . CODES, page 237-242. ACM, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Chakrabarty, Krishnendu
add a person with the name Chakrabarty, Krishnendu
 

Other publications of authors with the same name

An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications., , , and . J. Low Power Electronics, 10 (3): 506-518 (2014)On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics., , , and . VDAT, volume 382 of Communications in Computer and Information Science, page 274-283. Springer, (2013)Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.. DFT, IEEE Computer Society, (2006)Test Infrastructure Design - for Digital, Mixed-Signal and Hierarchical SOCs., and . LAP Lambert Academic Publishing, (2011)Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits.. Embedded Systems Handbook, CRC Press, (2005)Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip., , , and . VLSI Design, page 171-176. IEEE Computer Society, (2011)Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts., , and . J. Electronic Testing, 28 (2): 243-255 (2012)Guest Editorial.. J. Electronic Testing, 18 (4-5): 363 (2002)Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults., , , , , and . J. Electronic Testing, 29 (1): 35-48 (2013)Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (9): 1523-1536 (2015)