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Logical Time at Work: Capturing Data Dependencies and Platform Constraints.

, , and . FDL, page 241-. ECSI, Electronic Chips & Systems design Initiative, (2010)

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Dealing with AADL End-to-End Flow Latency with UML MARTE., , and . ICECCS, page 228-233. IEEE Computer Society, (2008)A multiform time approach to real-time system modeling; Application to an automotive system., , and . SIES, page 234-241. IEEE, (2007)Formal Specification of Hybrid MARTE Statecharts., , , , and . TASE, page 59-66. IEEE Computer Society, (2012)The Time Model of Logical Clocks Available in the OMG MARTE Profile., , , and . Synthesis of Embedded Software, Springer, (2010)Meta-models Combination for Reusing Verification Techniques., , and . MODELSWARD, page 37-48. SciTePress, (2019)xSHS: An Executable Domain-Specific Modeling Language for Modeling Stochastic and Hybrid Behaviors of Cyber-Physical Systems., , , and . APSEC, page 683-687. IEEE, (2018)UML Profile for MARTE: Time Model and CCSL.. ICTERI, volume 1000 of CEUR Workshop Proceedings, page 289-294. CEUR-WS.org, (2013)Clocks Model for Specification and Analysis of Timing in Real-Time Embedded Systems., , , and . ICTERI, volume 1000 of CEUR Workshop Proceedings, page 475-489. CEUR-WS.org, (2013)Work-in-Progress: From Logical Time Scheduling to Real-Time Scheduling., and . RTSS, page 143-146. IEEE Computer Society, (2018)MARTE/pCCSL: Modeling and Refining Stochastic Behaviors of CPSs with Probabilistic Logical Clocks., , , , and . FACS, volume 10231 of Lecture Notes in Computer Science, page 111-133. (2016)