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The Time Model of Logical Clocks Available in the OMG MARTE Profile.

, , , and . Synthesis of Embedded Software, Springer, (2010)

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Behavioral Specification of a Circuit Using SyncCharts: A Case Study., and . EUROMICRO, page 1091-. IEEE Computer Society, (2000)Use of the Behaviour Equivalence in Place-Transition Net Analysis.. Selected Papers from the First and the Second European Workshop on Application and Theory of Petri Nets, volume 52 of Informatik-Fachberichte, page 241-250. Springer, (1981)Leveraging Patterns on Domain Models to Improve UML Profile Definition., , , , and . FASE, volume 4961 of Lecture Notes in Computer Science, page 116-130. Springer, (2008)Modeling Time(s)., , and . MoDELS, volume 4735 of Lecture Notes in Computer Science, page 559-573. Springer, (2007)From UML to Petri Nets for non functional Property Verification., , and . IES, page 1-9. IEEE, (2006)VHDL Observers for Clock Constraint Checking., , and . SIES, page 98-107. IEEE, (2010)Executing AADL Models with UML/MARTE., , and . ICECCS, page 371-376. IEEE Computer Society, (2009)IP-XACT components with abstract time characterization., , , and . FDL, page 1-6. IEEE, (2009)Structural Transformations Giving B-Equivalent PT-Nets.. European Workshop on Applications and Theory of Petri Nets, volume 66 of Informatik-Fachberichte, page 14-28. Springer, (1982)On the Semantics of UML/MARTE Clock Constraints., and . ISORC, page 305-312. IEEE Computer Society, (2009)