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Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems., , , , and . IBM Journal of Research and Development, 57 (1/2): 4 (2013)Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors., , , , , , , , , and 1 other author(s). HPCA, page 238-242. IEEE Computer Society, (2005)Power-efficient, reliable microprocessor architectures: modeling and design methods., , , , , , , , , and 5 other author(s). ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2010)Microarchitectural techniques for power gating of execution units., , , , , and . ISLPED, page 32-37. ACM, (2004)Corrections To application-specific Programmable Control For High-performance Asynchronous Circuits., and . Proc. IEEE, 87 (3): 525 (1999)Quantifying sources of error in McPAT and potential impacts on architectural studies., , , , and . HPCA, page 577-589. IEEE Computer Society, (2015)High-Level Asynchronous System Design Using the ACK Framework., , , and . ASYNC, page 93-103. IEEE Computer Society, (2000)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , and 6 other author(s). PACS, volume 2325 of Lecture Notes in Computer Science, page 1-17. Springer, (2002)Efficient algorithms for exact two-level hazard-free logic minimization., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (11): 1269-1283 (2002)Efficient Exact Two-Level Hazard-Free Logic Minimization., and . ASYNC, page 64-73. IEEE Computer Society, (2001)