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Power-efficient, reliable microprocessor architectures: modeling and design methods.

P. Bose, A. Buyuktosunoglu, C. Cher, J. Darringer, M. Gupta, H. Hamann, H. Jacobson, P. Kudva, E. Kursun, N. Madan, I. Nair, J. Rivers, J. Shin, A. Weger, and V. Zyuban. ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2010)

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Automated detection and verification of parity-protected memory elements.E. Arbel, S. Koyfman, P. Kudva, and S. Moran. ICCAD, page 1-8. IEEE, (2014)Stable Adaptive Schemes for System Identification and Control - Part II.K. Narendra, and P. Kudva. IEEE Trans. Systems, Man, and Cybernetics, 4 (6): 552-560 (1974)Measurements for structural logic synthesis optimizations.P. Kudva, A. Sullivan, and W. Dougherty. IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (6): 665-674 (2003)Testing two-phase transition signaling based self-timed circuits in a synthesis environment.P. Kudva, and V. Akella. HLSS, page 104-111. ACM, (1994)Statistical Fault Injection.P. Ramachandran, P. Kudva, J. Kellington, J. Schumann, and P. Sanda. DSN, page 122-127. IEEE Computer Society, (2008)Implicit enumeration of structural changes in circuit optimization.V. Kravets, and P. Kudva. DAC, page 438-441. ACM, (2004)Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.H. Naeimi, S. Natarajan, K. Vaid, P. Kudva, and M. Natu. VTS, page 1. IEEE Computer Society, (2013)Rethinking Processor Design: Parameter Correlations.N. Sam, S. McKee, and P. Kudva. ICECS, page 156-159. IEEE, (2006)Soft-error resilience of the IBM POWER6 processor input/output subsystem.C. Bender, P. Sanda, P. Kudva, R. Mata, V. Pokala, R. Haraden, and M. Schallhorn. IBM Journal of Research and Development, 52 (3): 285-292 (2008)Combinatorial cell design for CMOS libraries.F. Beeftink, P. Kudva, D. Kung, R. Puri, and L. Stok. Integration, 29 (1): 67-93 (2000)

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Power-efficient, reliable microprocessor architectures: modeling and design methods.

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Disambiguation of "Kudva, Prabhakar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power-efficient, reliable microprocessor architectures: modeling and design methods.

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Power-efficient, reliable microprocessor architectures: modeling and design methods.