PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Mutlu, Onur"

Author of the publication

copydeleteadd this publication to your clipboard
Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field.

, , , and . DSN, page 415-426. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Mutlu, Onur
add a person with the name Mutlu, Onur
 

Other publications of authors with the same name

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM., , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor., , , , , , , , , and 3 other author(s). IEEE Micro, 36 (4): 70-85 (2016)Zorua: A holistic approach to resource virtualization in GPUs., , , , , , , , and . MICRO, page 1-14. IEEE Computer Society, (2016)Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field., , , and . DSN, page 415-426. IEEE Computer Society, (2015)Aérgia: A Network-on-Chip Exploiting Packet Latency Slack., , , and . IEEE Micro, 31 (1): 29-41 (2011)The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost., , , , and . ICCD, page 8-15. IEEE Computer Society, (2014)Techniques for Efficient Processing in Runahead Execution Engines., , and . ISCA, page 370-381. IEEE Computer Society, (2005)Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling., , , and . DATE, page 1285-1290. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks., , and . ISQED, page 475-484. IEEE, (2015)HAT: Heterogeneous Adaptive Throttling for On-Chip Networks., , , and . SBAC-PAD, page 9-18. IEEE Computer Society, (2012)