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Disambiguation of "Patt, Yale N."

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Techniques for Efficient Processing in Runahead Execution Engines.

, , and . ISCA, page 370-381. IEEE Computer Society, (2005)

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Jan-Philipp Negel

Thin-disk multipass amplifier for fs pulses delivering 400 W of average and 2.0 GW of peak power for linear polarization as well as 235 W and 1.2 GW for radial polarization, , , , , , , and . Applied Physics. B, Lasers and optics, 123 (5): 156 (2017)

Univ. -Prof. Ph. D. Mathias Niepert University of Stuttgart

Vectorized Conditional Neural Fields: A Framework for Solving Time-dependent Parametric Partial Differential Equations, , , and . In Proceedings of the 41st International Conference on Machine Learning (ICML 2024), OpenReview.net, (2024)

none

Alexander Naubert

Dr. phil. Michael Nerurkar University of Stuttgart

 

Other publications of authors with the same name

An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors., , , and . IEEE Trans. Computers, 54 (12): 1556-1571 (2005)Checkpoint Repair for High-Performance Out-of-Order Execution Machines., and . IEEE Trans. Computers, 36 (12): 1496-1514 (1987)Highest performance computing machines.. Microprocessing and Microprogramming, 35 (1-5): 1 (1992)Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication., , , and . IEEE Micro, 27 (1): 94-104 (2007)Wish Branches: Enabling Adaptive and Aggressive Predicated Execution., , , and . IEEE Micro, 26 (1): 48-58 (2006)The future of simulation: A field of dreams., , , and . ISPASS, page 169. IEEE Computer Society, (2004)Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?. ISCA, page 2. IEEE Computer Society, (2006)Alternative implementations of Prolog: the microarchitecture perspective.. IEEE Trans. Systems, Man, and Cybernetics, 19 (4): 693-698 (1989)Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution., , , and . International Journal of Parallel Programming, 25 (5): 363-383 (1997)Enhancing instruction scheduling with a block-structured ISA., and . International Journal of Parallel Programming, 23 (3): 221-243 (1995)