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Disambiguation of "López, Sonia"

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Designing customized ISA processors using high level synthesis.

, , , and . ReConFig, page 1-6. IEEE, (2015)

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Dr. -Ing. Juan Santiago López Bermúdez University of Stuttgart

Dr. phil. Sonia D'Souza University of Stuttgart

Rodrigo Lopez Portillo Alcocer University of Stuttgart

Jonathan Hernandez Lopez University of Stuttgart

Sara Suarez Lopez University of Stuttgart

 

Other publications of authors with the same name

Designing customized ISA processors using high level synthesis., , , and . ReConFig, page 1-6. IEEE, (2015)A phase adaptive cache hierarchy for SMT processors., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (8): 683-694 (2011)Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization., , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 151-160. Springer, (2003)Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA., , and . ReConFig, page 1-7. IEEE, (2013)Enabling FPGA support in Matlab based heterogeneous systems., , , and . ReConFig, page 1-6. IEEE, (2014)A Parallelizing Matlab Compiler Framework and Run Time for Heterogeneous Systems., , , and . HPCC/CSS/ICESS, page 232-237. IEEE, (2015)Performance modeling of pipelined linear algebra architectures on FPGAs., , and . Computers & Electrical Engineering, 40 (4): 1015-1027 (2014)Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions., , , , , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 495-505. Springer, (2006)Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs., , , , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 146-153. Springer, (2013)Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches., , , , and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 136-150. Springer, (2007)