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A phase adaptive cache hierarchy for SMT processors.

, , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (8): 683-694 (2011)

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Miss Rate Prediction Across Program Inputs and Cache Configurations., , , , and . IEEE Trans. Computers, 56 (3): 328-343 (2007)Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors., , , , and . PACT, page 416. IEEE Computer Society, (2007)Tashkent: uniting durability with transaction ordering for high-performance scalable database replication., , and . EuroSys, page 117-130. ACM, (2006)Hiding Synchronization Delays in a GALS Processor Microarchitecture., , , , , and . ASYNC, page 159-169. IEEE Computer Society, (2004)A phase adaptive cache hierarchy for SMT processors., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (8): 683-694 (2011)Caching Dynamic Web Content: Designing and Analysing an Aspect-Oriented Solution., , , , and . Middleware, volume 4290 of Lecture Notes in Computer Science, page 1-21. Springer, (2006)Adaptive Cache Memories for SMT Processors., , , , , and . DSD, page 331-338. IEEE Computer Society, (2010)Tashkent+: memory-aware load balancing and update filtering in replicated databases., , and . EuroSys, page 399-412. ACM, (2007)Predicting replicated database scalability from standalone database profiling., , , and . EuroSys, page 303-316. ACM, (2009)Dynamically Trading Frequency for Complexity in a GALS Microprocessor., , , , and . MICRO, page 157-168. IEEE Computer Society, (2004)