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Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

I. Boybat, C. di Nolfo, S. Ambrogio, M. Bodini, N. Farinha, R. Shelby, P. Narayanan, S. Sidler, H. Tsai, Y. Leblebici, and G. Burr. ICRC, page 1-8. IEEE, (2017)

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Parameter variation sensing and estimation in nanoscale fabrics.J. Zhang, M. Rahman, P. Narayanan, S. Khasanvis, and C. Moritz. J. Parallel Distrib. Comput., 74 (6): 2504-2511 (2014)Towards a framework for designing applications onto hybrid nano/CMOS fabrics.C. Dezan, C. Teodorov, L. Lagadec, M. Leuchtenburg, T. Wang, P. Narayanan, and C. Moritz. Microelectronics Journal, 40 (4-5): 656-664 (2009)CMOS Control Enabled Single-Type FET NASIC.P. Narayanan, M. Leuchtenburg, T. Wang, and C. Moritz. ISVLSI, page 191-196. IEEE Computer Society, (2008)Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.P. Vijayakumar, P. Narayanan, I. Koren, C. Krishna, and C. Moritz. NANOARCH, page 181-188. IEEE Computer Society, (2011)Validating cascading of crossbar circuits with an integrated device-circuit exploration.P. Narayanan, C. Moritz, K. won Park, and C. Chui. NANOARCH, page 37-42. IEEE Computer Society, (2009)Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory.P. Narayanan, A. Fumarola, L. Sanches, K. Hosokawa, S. Lewis, R. Shelby, and G. Burr. IBM Journal of Research and Development, 61 (4): 11 (2017)Metal-Gated Junctionless Nanowire Transistors.M. Rahman, P. Narayanan, and C. Moritz. CoRR, (2014)Nanowire field-programmable computing platform.S. Khasanvis, M. Rahman, P. Shabadi, P. Narayanan, H. Yu, C. Chui, and C. Moritz. NANOARCH, page 23-25. IEEE Computer Society, (2013)Programmable cellular architectures at the nanoscale.P. Narayanan, T. Wang, and C. Moritz. Nano Comm. Netw., 1 (2): 77-85 (2010)Deep Learning with Limited Numerical Precision.S. Gupta, A. Agrawal, K. Gopalakrishnan, and P. Narayanan. ICML, volume 37 of JMLR Workshop and Conference Proceedings, page 1737-1746. JMLR.org, (2015)

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Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

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Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.