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Disambiguation of "Hiramoto, Toshiro"

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Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers.

, , , , , , , , and . 3DIC, page TS9.2.1-TS9.2.4. IEEE, (2015)

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Other publications of authors with the same name

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress., , , and . IEICE Transactions, 96-C (6): 759-765 (2013)New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment., , , , , , , , , and 10 other author(s). VLSI Circuits, page 105-106. IEEE, (2018)VTCMOS characteristics and its optimum conditions predicted by a compact analytical model., , , , and . ISLPED, page 123-128. ACM, (2001)Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations., , , and . IEICE Transactions, 90-C (4): 836-841 (2007)Emerging nanoscale silicon devices taking advantage of nanostructure physics., , and . IBM Journal of Research and Development, 50 (4-5): 411-418 (2006)Ultra-low-voltage operation: device perspective.. ISLPED, page 59-60. IEEE/ACM, (2011)NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM., , , , and . IEICE Transactions, 96-C (5): 620-623 (2013)Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) Commentary., , , , , , and . IEEE Technol. Soc. Mag., 34 (2): 21-30 (2015)Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs., , , , and . CICC, page 1-4. IEEE, (2011)VTCMOS characteristics and its optimum conditions predicted by a compact analytical model., , , , and . IEEE Trans. VLSI Syst., 11 (5): 755-761 (2003)