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Disambiguation of "Mutlu, Onur"

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Evaluating Row Buffer Locality in Future Non-Volatile Main Memories.

, , and . CoRR, (2018)

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Other publications of authors with the same name

Aérgia: A Network-on-Chip Exploiting Packet Latency Slack., , , and . IEEE Micro, 31 (1): 29-41 (2011)Prefetch-Aware DRAM Controllers., , , and . MICRO, page 200-209. IEEE Computer Society, (2008)Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution., , , and . MICRO, page 43-54. IEEE Computer Society, (2005)Express Cube Topologies for on-Chip Interconnects., , , and . HPCA, page 163-174. IEEE Computer Society, (2009)Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers., , , and . HPCA, page 63-74. IEEE Computer Society, (2007)Techniques for Efficient Processing in Runahead Execution Engines., , and . ISCA, page 370-381. IEEE Computer Society, (2005)Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling., , , and . DATE, page 1285-1290. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks., , and . ISQED, page 475-484. IEEE, (2015)HAT: Heterogeneous Adaptive Throttling for On-Chip Networks., , , and . SBAC-PAD, page 9-18. IEEE Computer Society, (2012)The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost., , , , and . ICCD, page 8-15. IEEE Computer Society, (2014)