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Disambiguation of "Colburn, Jonathon E."

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Dynamic docking architecture for concurrent testing and peak power reduction.

, , , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)

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E. Zafeiriou

E. Garrelts

P. E. Bl\"ochl

Andr{\'{e}} Buchau

Umm-E Habiba University of Stuttgart

 

Other publications of authors with the same name

Enhancing testability by structured partial scan., , and . VTS, page 152-157. IEEE Computer Society, (2012)Flexible scan interface architecture for complex SoCs., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)XLBIST: X-Tolerant Logic BIST., , , and . ITC, page 1-9. IEEE, (2018)Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis., , , , , and . MTDT, page 48-53. IEEE Computer Society, (1999)Two-level compression through selective reseeding., , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)Achieving extreme scan compression for SoC Designs., , , and . ITC, page 1-8. IEEE Computer Society, (2014)Optimizing Memory Tests by Analyzing Defect Coverage., , , and . MTDT, page 20-28. IEEE Computer Society, (2000)Hybrid selector for high-X scan compression., , , and . ITC, page 1-10. IEEE Computer Society, (2012)Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis., , and . ITC, page 1065-1072. IEEE Computer Society, (1999)Dynamic docking architecture for concurrent testing and peak power reduction., , , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)