%0 Conference Paper %1 conf/vts/SonawaneJCSYSNC16 %A Sonawane, Milind %A Jagannadha, Pavan Kumar Datla %A Chadalavada, Sailendra %A Sarangi, Shantanu %A Yilmaz, Mahmut %A Sanghani, Amit %A Natarajan, Karthikeyan %A Colburn, Jonathon E. %A Sinha, Anubhav %B VTS %D 2016 %I IEEE Computer Society %K dblp %P 1-6 %T Dynamic docking architecture for concurrent testing and peak power reduction. %U http://dblp.uni-trier.de/db/conf/vts/vts2016.html#SonawaneJCSYSNC16 %@ 978-1-4673-8454-4

@inproceedings{conf/vts/SonawaneJCSYSNC16, added-at = {2016-06-09T00:00:00.000+0200}, author = {Sonawane, Milind and Jagannadha, Pavan Kumar Datla and Chadalavada, Sailendra and Sarangi, Shantanu and Yilmaz, Mahmut and Sanghani, Amit and Natarajan, Karthikeyan and Colburn, Jonathon E. and Sinha, Anubhav}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/29fe46f93159714d0524a2c0f035739b9/dblp}, booktitle = {VTS}, crossref = {conf/vts/2016}, ee = {http://doi.ieeecomputersociety.org/10.1109/VTS.2016.7477290}, interhash = {b6f7ad060aff786631967a099384e21b}, intrahash = {9fe46f93159714d0524a2c0f035739b9}, isbn = {978-1-4673-8454-4}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE Computer Society}, timestamp = {2016-06-10T09:33:06.000+0200}, title = {Dynamic docking architecture for concurrent testing and peak power reduction.}, url = {http://dblp.uni-trier.de/db/conf/vts/vts2016.html#SonawaneJCSYSNC16}, year = 2016 }