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Disambiguation of "Perkowski, Marek A."

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High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?

, , , and . Multiple-Valued Logic and Soft Computing, 20 (1-2): 89-120 (2012)

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A. Laukemann

A. Laukemann

A. Laukemann

A. Vo{\ss}

A. Afkari

 

Other publications of authors with the same name

A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits., , and . IEEE Trans. Computers, 49 (3): 267-276 (2000)Quantum ternary parallel adder/subtractor with partially-look-ahead carry., and . Journal of Systems Architecture, 53 (7): 453-464 (2007)Fundamentals of Reversible Logic and Computing., and . DSD, page 244. IEEE Computer Society, (2001)Bi-Directional Synthesis of 4-Bit Reversible Circuits., , , and . Comput. J., 51 (2): 207-215 (2008)Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping., and . EURO-DAC, page 8-13. IEEE Computer Society, (1994)A Constructive Algorithm for Reversible Logic Synthesis., , , , and . IEEE Congress on Evolutionary Computation, page 2416-2421. IEEE, (2006)Synthesis of quantum arrays with low quantum costs from Kronecker Functional Lattice Diagrams., and . IEEE Congress on Evolutionary Computation, page 1-7. IEEE, (2010)Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates., and . IEEE Congress on Evolutionary Computation, page 2194-2201. IEEE, (2004)Quantum Finite State Machines as Sequential Quantum Circuits., and . ISMVL, page 92-97. IEEE Computer Society, (2009)Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays., and . ISMVL, page 32-37. IEEE Computer Society, (1998)