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A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.

, , and . IEEE Trans. Computers, 49 (3): 267-276 (2000)

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Fundamentals of Reversible Logic and Computing., and . DSD, page 244. IEEE Computer Society, (2001)Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping., and . EURO-DAC, page 8-13. IEEE Computer Society, (1994)A Cost Minimization Approach to Synthesis of Linear Reversible Circuits., and . CoRR, (2014)Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits., , and . VLSI Design, 2002 (1): 107-122 (2002)Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits., , , and . CIAA, volume 4094 of Lecture Notes in Computer Science, page 279-280. Springer, (2006)Multiple-Valued Generalized Reed-Muller Forms., and . ISMVL, page 40-48. IEEE Computer Society, (1991)Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications., , and . ISMVL, page 50-58. IEEE Computer Society, (1999)Fault Models for Quantum Mechanical Switching Networks., , and . J. Electronic Testing, 26 (5): 499-511 (2010)A Group Algebraic Approach to NPN Classification of Boolean Functions., , , , , and . Theory Comput. Syst., 63 (6): 1278-1297 (2019)Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates., and . IEEE Congress on Evolutionary Computation, page 2194-2201. IEEE, (2004)