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Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.

M. Jamaa, K. Moselund, D. Atienza, D. Bouvet, A. Ionescu, Y. Leblebici, and G. Micheli. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (11): 2053-2067 (2008)

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Dr. Marie Davidova University of Stuttgart

David Inkermann

David Briesenick University of Stuttgart

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Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.D. Atienza, S. Mamagkakis, F. Catthoor, J. Mendias, and D. Soudris. DATE, page 532-537. IEEE Computer Society, (2004)Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice-Parallel Video Decoders on Multicore Systems.N. Mastronarde, K. Kanoun, D. Atienza, P. Frossard, and M. van der Schaar. IEEE Trans. Multimedia, 15 (2): 268-278 (2013)A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.M. Jamaa, D. Atienza, Y. Leblebici, and G. Micheli. ASP-DAC, page 835-840. IEEE, (2009)A control theory approach for thermal balancing of MPSoC.F. Zanini, D. Atienza, and G. Micheli. ASP-DAC, page 37-42. IEEE, (2009)Run-time adaptable on-chip thermal triggers.P. Kumar, and D. Atienza. ASP-DAC, page 255-260. IEEE, (2011)Markov decision process based energy-efficient scheduling for slice-parallel video decoding.N. Mastronarde, K. Kanoun, D. Atienza, and M. van der Schaar. ICME Workshops, page 1-6. IEEE Computer Society, (2013)Efficient Hardware Design of Iterative Stencil Loops.V. Rana, I. Beretta, F. Bruschi, A. Nacci, D. Atienza, and D. Sciuto. IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (12): 2018-2031 (2016)HW-SW emulation framework for temperature-aware design in MPSoCs.D. Atienza, P. Valle, G. Paci, F. Poletti, L. Benini, G. Micheli, J. Mendias, and R. Hermida. ACM Trans. Design Autom. Electr. Syst., (2007)A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.P. Valle, D. Atienza, I. Magan, J. Flores, E. Perez, J. Mendias, L. Benini, and G. Micheli. VLSI-SoC, page 140-145. IEEE, (2006)A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.S. Murali, D. Atienza, L. Benini, and G. Micheli. VLSI Design, (2007)