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Disambiguation of "Huang, Jiun-Lang"

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Improved weight assignment for logic switching activity during at-speed test pattern generation.

, , , , , and . ASP-DAC, page 493-498. IEEE, (2010)

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Dr. rer. nat. Nicolai Lang University of Stuttgart

Lukas Lang University of Stuttgart

Jingjing Huang University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Dr. -Ing. Min Huang University of Stuttgart

 

Other publications of authors with the same name

A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays., and . JCP, 4 (4): 338-346 (2009)FPGA-Based Subset Sum Delay Lines., , , and . ATS, page 287-291. IEEE Computer Society, (2014)CSER: BISER-based concurrent soft-error resilience., , , , , and . VTS, page 153-158. IEEE Computer Society, (2010)An ADC/DAC loopback testing methodology by DAC output offsetting and scaling., and . VTS, page 289-294. IEEE Computer Society, (2010)SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator., , , and . ATS, page 43-48. IEEE Computer Society, (2015)PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment., , and . ATS, page 391-396. IEEE Computer Society, (2008)On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs., , , , , , , , , and . DFT, page 143-151. IEEE Computer Society, (2008)Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs., , , and . J. Electronic Testing, 27 (4): 441-453 (2011)Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (11): 1767-1776 (2009)Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 48:1-48:16 (2012)