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Disambiguation of "Leblebici, Yusuf"

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3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.

, , , , and . VLSI-SoC, page 30-35. IEEE, (2012)

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Other publications of authors with the same name

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS., , and . VLSIC, page 180-. IEEE, (2015)ILLIADS: a fast timing and reliability simulator for digital MOS circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (9): 1387-1402 (1993)Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity., , and . ISCAS (5), page 453-456. IEEE, (2003)Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants., , , , , , and . ISCAS, page 533-536. IEEE, (2009)Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders., , , , and . ISCAS, page 1772-1775. IEEE, (2011)Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage., and . ISCAS, page 1871-1874. IEEE, (2007)Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors., and . ISCAS (3), page 685-688. IEEE, (2004)A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories., , , and . ASP-DAC, page 835-840. IEEE, (2009)Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)