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Timing margin evaluation with a simple statistical timing analysis flow.

, , , , , and . J. Embedded Computing, 3 (3): 221-229 (2009)

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Yield Enhancement Methodology for CMOS Standard Cells., , , , , , , and . ISQED, page 497-502. IEEE Computer Society, (2006)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1677-1684 (2006)A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI., , , and . J. Low Power Electronics, 14 (3): 404-413 (2018)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , and . J. Solid-State Circuits, 49 (7): 1499-1505 (2014)An Open Platform for Developing Multiprocessor SoCs., , , , , , and . IEEE Computer, 38 (7): 60-67 (2005)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology., , , , , , , , , and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)Statistical Characterization of Library Timing Performance., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)Product On-Chip Process Compensation for Low Power and Yield Enhancement., , , , , , , , , and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)Clockless Design Performance Monitoring for Nanometer Technologies., , , , and . ASYNC, page 108-109. IEEE Computer Society, (2014)Temperature Dependency in UDSM Process., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 693-703. Springer, (2005)