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Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.

M. Katevenis, R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, J. Pascual, J. Navaridas, M. Luján, J. Goodacre, B. Lietzow, and M. Kersten. Microprocessors and Microsystems - Embedded Hardware Design, (2018)

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User-Level DMA without Operating System Kernel Modification.E. Markatos, and M. Katevenis. HPCA, page 322-331. IEEE Computer Society, (1997)FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, M. Katevenis, D. Pnevmatikatos, and X. Yang. ICSAMOS, page 149-156. IEEE, (2009)Discharging the Network From Its Flow Control Headaches: Packet Drops and HOL Blocking.N. Chrysos, L. Chen, C. Kachris, and M. Katevenis. IEEE/ACM Trans. Netw., 24 (1): 15-28 (2016)Building an FoC Using Large, Buffered Crossbar Cores.D. Simos, I. Papaefstathiou, and M. Katevenis. IEEE Design & Test of Computers, 25 (6): 538-548 (2008)ATLAS I: implementing a single-chip ATM switch with backpressure.G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, D. Mavroidis, D. Serpanos, and M. Katevenis. IEEE Micro, 19 (1): 30-41 (1999)Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs.S. Kavadias, M. Katevenis, M. Zampetakis, and D. Nikolopoulos. International Journal of Parallel Programming, 40 (6): 583-604 (2012)VLSI micro-architectures for high-radix crossbar schedulers.G. Passas, M. Katevenis, and D. Pnevmatikatos. NOCS, page 217-224. ACM/IEEE Computer Society, (2011)Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface.C. Kachris, G. Nikiforos, S. Kavadias, V. Papaefstathiou, and M. Katevenis. ReConFig, page 328-333. IEEE Computer Society, (2010)The Next Generation of Exascale-Class Systems: The ExaNeSt Project.R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, F. Simula and 8 other author(s). DSD, page 510-515. IEEE Computer Society, (2017)EUROSERVER: Energy Efficient Node for European Micro-Servers.Y. Durand, P. Carpenter, S. Adami, A. Bilas, D. Dutoit, A. Farcy, G. Gaydadjiev, J. Goodacre, M. Katevenis, M. Marazakis and 3 other author(s). DSD, page 206-213. IEEE Computer Society, (2014)

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Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.

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Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.