Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.

G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, M. Katevenis, D. Pnevmatikatos, and X. Yang. ICSAMOS, page 149-156. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Papaefstathiou, Vassilis

add a person with the name Papaefstathiou, Vassilis

Other publications of authors with the same name

Prototyping Efficient Interprocessor Communication Mechanisms.V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, and M. Katevenis. ICSAMOS, page 26-33. IEEE, (2007)Design space exploration for fair resource-allocated NoC architectures.A. Psathakis, V. Papaefstathiou, M. Katevenis, and D. Pnevmatikatos. ICSAMOS, page 141-148. IEEE, (2014)A Systematic Evaluation of Emerging Mesh-like CMP NoCs.A. Psathakis, V. Papaefstathiou, N. Chrysos, F. Chaix, E. Vasilakis, D. Pnevmatikatos, and M. Katevenis. ANCS, page 159-170. IEEE Computer Society, (2015)An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks.I. Papaefstathiou, and V. Papaefstathiou. ICC, page 211-216. IEEE, (2006)Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache.E. Vasilakis, V. Papaefstathiou, P. Trancoso, and I. Sourdis. TACO, 15 (4): 65:1-65:23 (2019)SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures.M. Azhar, P. Stenström, and V. Papaefstathiou. TACO, 14 (4): 41:1-41:25 (2017)Optimization and bottleneck analysis of network block I/O in commodity storage systems.M. Marazakis, V. Papaefstathiou, and A. Bilas. ICS, page 33-42. ACM, (2007)Explicit Communication and Synchronization in SARC.M. Katevenis, V. Papaefstathiou, S. Kavadias, D. Pnevmatikatos, F. Silla, and D. Nikolopoulos. IEEE Micro, 30 (5): 30-41 (2010)NP-SARC: Scalable network processing in the SARC multi-core FPGA platform.C. Kachris, G. Nikiforos, V. Papaefstathiou, S. Kavadias, and M. Katevenis. Journal of Systems Architecture - Embedded Systems Design, 59 (1): 39-47 (2013)FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards.S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou, I. Mavroidis, M. Katevenis, D. Pnevmatikatos, and D. Nikolopoulos. Journal of Systems Architecture - Embedded Systems Design, 60 (6): 481-493 (2014)

PUMA

Disambiguation of "Papaefstathiou, Vassilis"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Papaefstathiou, Vassilis"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.