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Prototyping Efficient Interprocessor Communication Mechanisms.

V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, and M. Katevenis. ICSAMOS, page 26-33. IEEE, (2007)

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An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks.I. Papaefstathiou, and V. Papaefstathiou. ICC, page 211-216. IEEE, (2006)Optimization and bottleneck analysis of network block I/O in commodity storage systems.M. Marazakis, V. Papaefstathiou, and A. Bilas. ICS, page 33-42. ACM, (2007)A Systematic Evaluation of Emerging Mesh-like CMP NoCs.A. Psathakis, V. Papaefstathiou, N. Chrysos, F. Chaix, E. Vasilakis, D. Pnevmatikatos, and M. Katevenis. ANCS, page 159-170. IEEE Computer Society, (2015)Prototyping Efficient Interprocessor Communication Mechanisms.V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, and M. Katevenis. ICSAMOS, page 26-33. IEEE, (2007)Design space exploration for fair resource-allocated NoC architectures.A. Psathakis, V. Papaefstathiou, M. Katevenis, and D. Pnevmatikatos. ICSAMOS, page 141-148. IEEE, (2014)Explicit Communication and Synchronization in SARC.M. Katevenis, V. Papaefstathiou, S. Kavadias, D. Pnevmatikatos, F. Silla, and D. Nikolopoulos. IEEE Micro, 30 (5): 30-41 (2010)Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache.E. Vasilakis, V. Papaefstathiou, P. Trancoso, and I. Sourdis. TACO, 15 (4): 65:1-65:23 (2019)SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures.M. Azhar, P. Stenström, and V. Papaefstathiou. TACO, 14 (4): 41:1-41:25 (2017)FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards.S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou, I. Mavroidis, M. Katevenis, D. Pnevmatikatos, and D. Nikolopoulos. Journal of Systems Architecture - Embedded Systems Design, 60 (6): 481-493 (2014)Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories.D. Knyaginin, V. Papaefstathiou, and P. Stenström. MEMSYS, page 121-132. ACM, (2016)

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Prototyping Efficient Interprocessor Communication Mechanisms.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Prototyping Efficient Interprocessor Communication Mechanisms.

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Prototyping Efficient Interprocessor Communication Mechanisms.