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Validation of hardware events for successful performance pattern identification in High Performance Computing.

T. Röhl, J. Eitzinger, G. Hager, and G. Wellein. CoRR, (2017)

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Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

Hierarchical hybrid grids: achieving TERAFLOP performance on large scale finite element simulations.B. Bergen, G. Wellein, F. Hülsemann, and U. Rüde. IJPEDS, 22 (4): 311-329 (2007)Performance analysis and optimization strategies for a D3Q19 lattice Boltzmann kernel on nVIDIA GPUs using CUDA.J. Habich, T. Zeiser, G. Hager, and G. Wellein. Advances in Engineering Software, 42 (5): 266-272 (2011)Pushing the limits for medical image reconstruction on recent standard multicore processors.J. Treibig, G. Hager, H. Hofmann, J. Hornegger, and G. Wellein. IJHPCA, 27 (2): 162-177 (2013)Performance and power for highly parallel systems.G. Hager, D. Kerbyson, A. Vishnu, and G. Wellein. Concurrency and Computation: Practice and Experience, 28 (2): 187-188 (2016)Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers.G. Hager, T. Zeiser, and G. Wellein. IPDPS, page 1-7. IEEE, (2008)Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory.M. Wittmann, G. Hager, and G. Wellein. IPDPS Workshops, page 1-7. IEEE, (2010)Chip-level and multi-node analysis of energy-optimized lattice Boltzmann CFD simulations.M. Wittmann, G. Hager, T. Zeiser, J. Treibig, and G. Wellein. Concurrency and Computation: Practice and Experience, 28 (7): 2295-2315 (2016)GHOST: Building Blocks for High Performance Sparse Linear Algebra on Heterogeneous Systems.M. Kreutzer, J. Thies, M. Röhrig-Zöllner, A. Pieper, F. Shahzad, M. Galgon, A. Basermann, H. Fehske, G. Hager, and G. Wellein. International Journal of Parallel Programming, 45 (5): 1046-1072 (2017)Multi-core architectures: Complexities of performance prediction and the impact of cache topologyJ. Treibig, G. Hager, and G. Wellein. CoRR, (2009)Domain decomposition and locality optimization for large-scale lattice Boltzmann simulationsM. Wittmann, T. Zeiser, G. Hager, and G. Wellein. CoRR, (2011)

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Disambiguation of "Wellein, Gerhard"

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Validation of hardware events for successful performance pattern identification in High Performance Computing.

Please choose a person to relate this publication to

Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Wellein, Gerhard"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Validation of hardware events for successful performance pattern identification in High Performance Computing.

Please choose a person to relate this publication to

Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
Harvard
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Validation of hardware events for successful performance pattern identification in High Performance Computing.