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Disambiguation of "Loi, Igor"

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An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.

, , , , , , , , , , , and . CoRR, (2016)

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Andrea Loi University of Stuttgart

PD Dr. Igor Shevchuk University of Stuttgart

Igor Hörner University of Stuttgart

Dr. phil. Igor Kristic University of Stuttgart

Lukas-Maximilian Loidold University of Stuttgart

 

Other publications of authors with the same name

Energy-efficient vision on the PULP platform for ultra-low power parallel computing., , , , and . SiPS, page 274-279. IEEE, (2014)A resilient architecture for low latency communication in shared-L1 processor clusters., , and . DATE, page 887-892. IEEE, (2012)Synthesis of low-overhead configurable source routing tables for network interfaces., , and . DATE, page 262-267. IEEE, (2009)Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters., , and . IEEE Trans. on Circuits and Systems, 59-II (12): 927-931 (2012)3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters., , and . NOCS, page 1-2. IEEE, (2013)The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores., , , , and . IEEE Trans. Multi-Scale Computing Systems, 4 (2): 99-112 (2018)Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing., , , , and . ESSCIRC, page 274-277. IEEE, (2018)A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing., , , , , and . IEEE Trans. on Circuits and Systems, 65-II (8): 1094-1098 (2018)3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory., , , , and . VLSI-SoC, page 30-35. IEEE, (2012)Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters., , , and . Conf. Computing Frontiers, page 15:1-15:10. ACM, (2014)