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A resilient architecture for low latency communication in shared-L1 processor clusters.

, , and . DATE, page 887-892. IEEE, (2012)

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De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs., , , and . DATE, page 1370-1373. ACM, (2008)Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification., , and . DSD, page 714-720. IEEE Computer Society, (2008)At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs., , and . IEEE Trans. Computers, 63 (3): 703-717 (2014)Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits., and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 131-140 (2011)Moonrake chip - GALS demonstrator in 40 nm CMOS technology., , , , , , , , and . SoC, page 9-13. IEEE, (2011)Reliable network-on-chip based on generalized de Bruijn graph., , , and . HLDVT, page 3-10. IEEE Computer Society, (2007)A resilient architecture for low latency communication in shared-L1 processor clusters., , and . DATE, page 887-892. IEEE, (2012)ReliNoC: A reliable network for priority-based on-chip communication., , and . DATE, page 667-672. IEEE, (2011)Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters., , and . IEEE Trans. on Circuits and Systems, 59-II (12): 927-931 (2012)HW/SW architecture for soft-error cancellation in real-time operating system., , , and . IEICE Electronic Express, 4 (23): 755-761 (2007)