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Covering conditions and algorithms for the synthesis of speed-independent circuits.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (3): 205-219 (1998)

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Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior., and . ASYNC, page 9-16. IEEE Computer Society, (2012)Technology mapping of timed circuits., , and . ASYNC, page 138-. IEEE Computer Society, (1995)Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing., and . ASYNC, page 75-82. IEEE Computer Society, (2013)An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates., and . IEEE Trans. VLSI Syst., 14 (9): 975-985 (2006)An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication., , and . ISCAS (5), page 361-364. IEEE, (2003)Sibling-substitution-based BDD minimization using don't cares., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (1): 44-55 (2000)Average-case technology mapping of asynchronous burst-mode circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (10): 1418-1434 (1999)Implicit enumeration of strongly connected components and anapplication to formal verification., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (10): 1225-1230 (2000)Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits., , , , , , , and . ASYNC, page 80-. IEEE Computer Society, (1998)Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415., , and . PATMOS, page 147-154. IEEE, (2018)