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Trace Buffer Attack: Security versus observability study in post-silicon debug., , and . VLSI-SoC, page 355-360. IEEE, (2015)Power-efficient Instruction Encoding Optimization for Embedded Processors., , , and . VLSI Design, page 595-600. IEEE Computer Society, (2007)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)Designing stream ciphers with scalable data-widths: a case study with HC-128., and . J. Cryptographic Engineering, 4 (2): 135-143 (2014)Design space exploration of partially re-configurable embedded processors., , , , , , and . DATE, page 319-324. EDA Consortium, San Jose, CA, USA, (2007)Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation., , , and . ICCD, page 193-199. IEEE Computer Society, (2005)Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs., , , , and . ISVLSI, page 619-624. IEEE Computer Society, (2016)Constructive Reversible Logic Synthesis for Boolean Functions with Special Properties., , , and . RC, volume 8507 of Lecture Notes in Computer Science, page 95-110. Springer, (2014)Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes., , and . IACR Cryptology ePrint Archive, (2018)A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates., , , and . IACR Cryptology ePrint Archive, (2017)