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Disambiguation of "Saito, Mitsuko"

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47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.

, , , , and . IEEE Trans. on Circuits and Systems, 57-I (9): 2269-2278 (2010)

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A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking., , , , , , , and . ISSCC, page 244-245. IEEE, (2009)A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking., , , , and . ISSCC, page 490-492. IEEE, (2011)A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking., , and . ISSCC, page 440-441. IEEE, (2010)An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM., , , and . ISSCC, page 436-437. IEEE, (2010)47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking., , , , , , and . CICC, page 449-452. IEEE, (2009)A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 249-256 (2012)A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×., , , and . ISSCC, page 214-215. IEEE, (2013)47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking., , , , and . IEEE Trans. on Circuits and Systems, 57-I (9): 2269-2278 (2010)2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking., , , , , , , and . J. Solid-State Circuits, 45 (1): 134-141 (2010)