Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Virazel, Arnaud
add a person with the name Virazel, Arnaud
 

Other publications of authors with the same name

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 540-549. Springer, (2005)A Design-for-Diagnosis Technique for SRAM Write Drivers., , , , , and . DATE, page 1480-1485. ACM, (2008)A concurrent approach for testing address decoder faults in eFlash memories., , , , , and . ITC, page 1-10. IEEE Computer Society, (2007)Testing approximate digital circuits: Challenges and opportunities., , , , and . LATS, page 1-6. IEEE, (2018)An effective ATPG flow for Gate Delay Faults., , , , , and . DTIS, page 1-6. IEEE, (2015)Is aproximate computing suitable for selective hardening of arithmetic circuits?, , , , and . DTIS, page 1-6. IEEE, (2018)Towards approximation during test of Integrated Circuits., , , , , and . DDECS, page 28-33. IEEE, (2017)A study of path delay variations in the presence of uncorrelated power and ground supply noise., , , , , and . DDECS, page 189-194. IEEE Computer Society, (2011)On using a SPICE-like TSTAC™ eFlash model for design and test., , , , , , , , and . DDECS, page 359-364. IEEE Computer Society, (2011)Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling., , , , , , and . DDECS, page 353-358. IEEE Computer Society, (2011)