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SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract.

, , , , and . DATE, page 358-363. IEEE Computer Society, (2004)

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Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework., , , and . J. Electronic Imaging, 23 (5): 053012 (2014)Low power methodology for an ASIC design flow based on high-level synthesis., , and . SoftCOM, page 11-15. IEEE, (2015)Solving the State Assignment Problem for Signal Transition Graphs., , , and . DAC, page 568-572. (1992)Generation of minimal size code for scheduling graphs., , and . DATE, page 668-673. IEEE Computer Society, (2001)Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform., , , and . DATE, page 10662-10667. IEEE Computer Society, (2003)Exploiting area/delay tradeoffs in high-level synthesis., , , and . DATE, page 1024-1029. IEEE, (2012)Realistic performance-constrained pipelining in high-level synthesis., , , and . DATE, page 1382-1387. IEEE, (2011)Quasi-static Scheduling for Concurrent Architectures., , , , and . Fundam. Inform., 62 (2): 171-196 (2004)Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL., and . ASYNC, page 84-92. IEEE Computer Society, (2000)Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis., , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)