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XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems., , , , , , , , and . PACT, page 75-86. ACM, (2012)The gem5 simulator., , , , , , , , , and 6 other author(s). SIGARCH Computer Architecture News, 39 (2): 1-7 (2011)Limits of Parallelism and Boosting in Dim Silicon., , , , , , and . IEEE Micro, 33 (5): 30-37 (2013)Swizzle-Switch Networks for Many-Core Systems., , , , , , , , , and 2 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 278-294 (2012)Assessing the performance limits of parallelized near-threshold computing., , , , , , and . DAC, page 1147-1152. ACM, (2012)Scaling towards kilo-core processors with asymmetric high-radix topologies., , , , , , , and . HPCA, page 496-507. IEEE Computer Society, (2013)A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS., , , , , , , and . ISSCC, page 478-480. IEEE, (2012)