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Disambiguation of "Oboril, Fabian"

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Towards Standardization of AV Safety: C++ Library for Responsibility Sensitive Safety.

, , , , , , , , , , , and . IV, page 2265-2271. IEEE, (2019)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Fabian Schnelle

Design and programming for cable-driven parallel robots in the German pavilion at the EXPO 2015, , , and . Machines, 3 (3): 223-241 (2015)

Fabian Schlichtherle University of Stuttgart

Guardians of the SAV – Security Measures for the Interior of Shared Automated Vehicles, , and . Posterbeitrag, (2024)

Dr. Fabian Schubö University of Stuttgart

Fabian Silber University of Stuttgart

Fabian Hampp University of Stuttgart

 

Other publications of authors with the same name

Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach., , , and . J. Low Power Electronics, 9 (4): 389-402 (2013)MTTF-balanced pipeline design., and . DATE, page 270-275. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Avoiding unnecessary write operations in STT-MRAM for low power implementation., , , and . ISQED, page 548-553. IEEE, (2014)ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level., and . DSN, page 1-12. IEEE Computer Society, (2012)Energy Efficient Scientific Computing on FPGAs using OpenCL., , , , and . FPGA, page 247-256. ACM, (2017)Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches., , , , , and . ISLPED, page 236-241. ACM, (2016)Aging-Aware Design of Microprocessor Instruction Pipelines., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (5): 704-716 (2014)Stress-aware P/G TSV planning in 3D-ICs., , , and . ASP-DAC, page 94-99. IEEE, (2015)Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Protecting caches against multi-bit errors using embedded erasure coding., , , , and . ETS, page 1-6. IEEE, (2015)