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Disambiguation of "U., Seng-Pan"

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A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW.

, , , , , and . ISCAS, page 373-376. IEEE, (2013)

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U. Schleinkofer

Qi Pan University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

 

Other publications of authors with the same name

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch., , , and . IEEE Trans. on Circuits and Systems, 55-II (7): 648-652 (2008)A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS., , , , , and . IEEE Trans. on Circuits and Systems, 57-II (1): 16-20 (2010)A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC., , , , , and . CICC, page 1-4. IEEE, (2012)Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals., , and . ICASSP (6), page 253-256. IEEE, (2003)A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC., , , and . ISCAS, page 1947-1950. IEEE, (2007)A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems., , and . ISCAS (1), page 369-372. IEEE, (2004)A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems., , and . ISCAS (1), page 320-323. IEEE, (2001)Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output., , , and . ISCAS (1), page 129-132. IEEE, (2003)Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity., , and . ISCAS (2), page 57-60. IEEE, (1999)A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation., , , , and . IEEE Trans. on Circuits and Systems, 63-II (7): 683-687 (2016)