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Disambiguation of "Sin, Sai-Weng"

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Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch.

, , , and . IEEE Trans. on Circuits and Systems, 55-II (7): 648-652 (2008)

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Simon Sailer University of Stuttgart

Dr. Cornelia Martina Sindermann University of Stuttgart

Oskar Wengrzyn University of Stuttgart

Ingeborg Wenger University of Stuttgart

Bhupender Kumar Saini University of Stuttgart

 

Other publications of authors with the same name

Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 537-547 (2015)A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer., , , , , and . ISCAS, page 65-68. IEEE, (2012)A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS., , , , , , , and . ISCAS, page 2239-2242. IEEE, (2013)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications., , , , , , and . ICECS, page 878-881. IEEE, (2010)A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators., , , , , and . ICECS, page 547-550. IEEE, (2010)A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators., , , , , and . APCCAS, page 1011-1014. IEEE, (2010)A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1410-1414 (2018)Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators., , , , , and . IEEE Trans. on Circuits and Systems, 63-II (9): 903-907 (2016)A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC., , , , and . J. Solid-State Circuits, 51 (2): 365-377 (2016)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , and . J. Solid-State Circuits, 47 (11): 2763-2772 (2012)