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Disambiguation of "Comte, Mariane"

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Testing for gate oxide short defects using the detectability interval paradigm.

, , , and . it - Information Technology, 56 (4): 173-181 (2014)

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Other publications of authors with the same name

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects., , , , , , and . European Test Symposium, page 113-118. IEEE Computer Society, (2008)An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects., , , , , , and . VTS, page 21-26. IEEE Computer Society, (2009)Accurate and efficient analytical electrical model of antenna for NFC applications., , , , , , , and . NEWCAS, page 1-4. IEEE, (2013)Which metrics to use for RF indirect test strategy?, , , , , and . SMACD, page 73-76. IEEE, (2019)Electrical Behavior of GOS Fault affected Domino Logic Cell., , , and . DELTA, page 183-189. IEEE Computer Society, (2006)Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations., , , , and . ISVLSI, page 164-169. IEEE Computer Society, (2016)ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator., , , , , , and . VLSI Design, (2008)MIRID: Mixed-Mode IR-Drop Induced Delay Simulator., , , , , and . Asian Test Symposium, page 177-182. IEEE Computer Society, (2013)A New Methodology For ADC Test Flow Optimization., , , , and . ITC, page 201-209. IEEE Computer Society, (2003)Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies., , , , and . J. Electronic Testing, 35 (1): 59-75 (2019)