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An Architectural Design For Parallel Fractal Compression.

, , , and . ASAP, page 3-11. IEEE Computer Society, (1996)

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Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline., , , and . ASAP, page 65-71. IEEE Computer Society, (1996)An Architectural Design For Parallel Fractal Compression., , , and . ASAP, page 3-11. IEEE Computer Society, (1996)Power comparisons for barrel shifters., , and . ISLPED, page 209-212. IEEE, (1996)A Parallel ASIC Architecture for Efficient Fractal Image Coding., , and . VLSI Signal Processing, 19 (2): 97-113 (1998)The MGAP Family of Processor Arrays., , , , and . Great Lakes Symposium on VLSI, page 105-. IEEE Computer Society, (1997)A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines., , , and . Great Lakes Symposium on VLSI, page 182-. IEEE Computer Society, (1997)