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TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies., , , , , , , and . FET, volume 7 of Procedia Computer Science, page 148-149. Elsevier, (2011)Implementing End-to-End Register Data-Flow Continuous Self-Test., , , , and . IEEE Trans. Computers, 60 (8): 1194-1206 (2011)Control-Flow Recovery Validation Using Microarchitectural Invariants., , , and . DFT, page 209-216. IEEE Computer Society, (2011)Optimizing cache miss equations polyhedra., , , and . SIGARCH Computer Architecture News, 28 (1): 43-52 (2000)Online error detection and correction of erratic bits in register files., , , , and . IOLTS, page 81-86. IEEE Computer Society, (2009)On-Line Failure Detection and Confinement in Caches., , , , and . IOLTS, page 3-9. IEEE Computer Society, (2008)On-line Failure Detection in Memory Order Buffers., , , and . ITC, page 1-10. IEEE Computer Society, (2008)Low Vccmin fault-tolerant cache with highly predictable performance., , , , and . MICRO, page 111-121. ACM, (2009)Electromigration for microarchitects., and . ACM Comput. Surv., 42 (2): 9:1-9:18 (2010)A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note)., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 194-198. Springer, (2000)