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An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design., and . IWSOC, page 55-58. IEEE Computer Society, (2004)Using an MDE Approach for Modeling of Interconnection Networks., , , and . ISPAN, page 289-294. IEEE Computer Society, (2008)Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design., , , , and . ISSS, page 26-31. ACM / IEEE Computer Society, (2002)A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization., , , , and . ISSPIT, page 528-531. IEEE Computer Society, (2010)SOAP Based Distributed Simulation Environment for SoC Design., , , , and . FDL, page 283-291. ECSI, (2005)Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation., , and . DASIP, page 68-75. IEEE, (2010)An optimal memory allocation for application-specific multiprocessor system-on-chip., , , and . ISSS, page 19-24. ACM / IEEE Computer Society, (2001)Massively parallel processing on a chip., , , , and . Conf. Computing Frontiers, page 277-286. ACM, (2007)A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design., , , , and . EURASIP J. Emb. Sys., (2011)A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme., , , , and . Integration, 46 (4): 404-412 (2013)