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Disambiguation of "Yang, Shiheng"

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A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.

, , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (9): 3307-3316 (2019)

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Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

 

Other publications of authors with the same name

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios., , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (9): 3307-3316 (2019)A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs., , , and . J. Solid-State Circuits, 54 (1): 88-98 (2019)A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS., , , , , and . J. Solid-State Circuits, 54 (5): 1351-1362 (2019)A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM., , , and . ISSCC, page 118-120. IEEE, (2018)Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (2): 495-505 (2022)A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level., , and . APCCAS, page 57-60. IEEE, (2014)A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur., , , , and . ISSCC, page 270-272. IEEE, (2019)A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC., , , , , , and . APCCAS, page 189-192. IEEE, (2021)A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS., , , , , and . ISSCC, page 450-452. IEEE, (2018)