%0 Conference Paper %1 conf/apccas/ZhouLWZYLL21 %A Zhou, Xiaodan %A Li, Zehao %A Wang, Yujie %A Zhou, Xiong %A Yang, Shiheng %A Liu, Jiaxin %A Li, Qiang %B APCCAS %D 2021 %I IEEE %K dblp %P 189-192 %T A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2021.html#ZhouLWZYLL21 %@ 978-1-6654-3916-9

@inproceedings{conf/apccas/ZhouLWZYLL21, added-at = {2022-02-11T00:00:00.000+0100}, author = {Zhou, Xiaodan and Li, Zehao and Wang, Yujie and Zhou, Xiong and Yang, Shiheng and Liu, Jiaxin and Li, Qiang}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d9554228ec7acddb8b32fb2ceebf1777/dblp}, booktitle = {APCCAS}, crossref = {conf/apccas/2021}, ee = {https://doi.org/10.1109/APCCAS51387.2021.9687731}, interhash = {92c1fe11b01c560957369ef6bd9b7b03}, intrahash = {d9554228ec7acddb8b32fb2ceebf1777}, isbn = {978-1-6654-3916-9}, keywords = {dblp}, pages = {189-192}, publisher = {IEEE}, timestamp = {2022-03-01T07:10:26.000+0100}, title = {A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2021.html#ZhouLWZYLL21}, year = 2021 }