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An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip., , and . Softw., Pract. Exper., 42 (7): 877-890 (2012)A 3D reconfigurable platform for 4G telecom applications., , and . DATE, page 555-558. IEEE, (2011)3D advanced integration technology for heterogeneous systems., , , , , , , , , and 4 other author(s). 3DIC, page FS6.1-FS6.3. IEEE, (2015)Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction).. Grenoble Institute of Technology, France, (1989)Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning., , , , , and . ETS, page 1-2. IEEE, (2019)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations., , , , , , and . 3DIC, page 1-5. IEEE, (2019)A VLSI implementation of parallel image reconstruction., and . CVGIP: Graphical Model and Image Processing, 53 (6): 581-591 (1991)An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs., , and . ISCAS, page 1222-1225. IEEE, (2015)Trends in complex SoC Design: From technology variability to multiprocessor architectures.. ICECS, page 1. IEEE, (2007)High level modelling and performance evaluation of address mapping in NAND flash memory., , and . ICECS, page 659-662. IEEE, (2009)