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Abstract Testing: Connecting Source Code Verification with Requirements.

, , , , and . QUATIC, page 89-96. IEEE Computer Society, (2010)

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A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL., and . Formal Methods in System Design, 7 (1/2): 73-99 (1995)Coverage Driven Verification applied to Embedded Software., , , , , , and . ISVLSI, page 159-164. IEEE Computer Society, (2007)Formal Specification in VHDL for Hardware Verification., , and . DATE, page 257-263. IEEE Computer Society, (1998)The simulation semantics of systemC., , , , , and . DATE, page 64-70. IEEE Computer Society, (2001)A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems., , , and . MBMV, page 11-20. HNI-Verlagsschriften, (1998)Beschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen., , , , , , , and . MBMV, page 161-170. Institut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock, (2013)Abstract Testing: Connecting Source Code Verification with Requirements., , , , and . QUATIC, page 89-96. IEEE Computer Society, (2010)Formal Data Analysis of Timed Finite State Systems., and . ECRTS, page 257-. IEEE Computer Society, (2002)Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path., , and . EDAC-ETC-EUROASIC, page 648-652. IEEE Computer Society, (1994)A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation., and . EDAC-ETC-EUROASIC, page 343-348. IEEE Computer Society, (1994)