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s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

Y. Hidaka, W. Gai, A. Hattori, T. Horie, J. Jiang, K. Kanda, Y. Koyanagi, S. Matsubara, and H. Osone. ISSCC, page 442-443. IEEE, (2007)

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Architecture of parallel management kernel for PIE64.Y. Hidaka, H. Koike, and H. Tanaka. Future Generation Comp. Syst., 10 (1): 29-43 (1994)A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.Y. Hidaka, W. Gai, A. Hattori, T. Horie, J. Jiang, K. Kanda, Y. Koyanagi, S. Matsubara, and H. Osone. ISSCC, page 442-443. IEEE, (2007)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.Y. Hidaka, T. Horie, Y. Koyanagi, T. Miyoshi, H. Osone, S. Parikh, S. Reddy, T. Shibuya, Y. Umezawa, and W. Walker. ISSCC, page 346-348. IEEE, (2011)A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.Y. Hidaka, W. Gai, T. Horie, J. Jiang, Y. Koyanagi, and H. Osone. J. Solid-State Circuits, 44 (12): 3547-3559 (2009)A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.Y. Hidaka, W. Gai, T. Horie, J. Jiang, Y. Koyanagi, and H. Osone. ISSCC, page 188-189. IEEE, (2009)A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS.Y. Lu, K. Jung, Y. Hidaka, and E. Alon. CICC, page 1-4. IEEE, (2012)Design Consideration of 6.25 Gbps Signaling for High-Performance Server.J. Jiang, W. Gai, A. Hattori, Y. Hidaka, T. Horie, Y. Koyanagi, and H. Osone. ASP-DAC, page 854-857. IEEE Computer Society, (2007)Architecture of Parallel Management Kernel for PIE64.Y. Hidaka, H. Koike, and H. Tanaka. PARLE, volume 605 of Lecture Notes in Computer Science, page 685-700. Springer, (1992)Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.Y. Lu, K. Jung, Y. Hidaka, and E. Alon. J. Solid-State Circuits, 48 (8): 1898-1909 (2013)A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.S. Parikh, T. Kao, Y. Hidaka, J. Jiang, A. Toda, S. McLeod, W. Walker, Y. Koyanagi, T. Shibuya, and J. Yamada. ISSCC, page 28-29. IEEE, (2013)

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A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

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A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.