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Disambiguation of "Terai, Masayuki"

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Min-cut placement with global objective functions for large scale sea-of-gates arrays.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 14 (4): 434-446 (1995)

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Other publications of authors with the same name

LORES - Logic Reorganization System., , , , , and . DAC, page 250-260. ACM, (1978)A new approach to over-the-cell channel routing with three layers., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (2): 187-200 (1994)An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2., , , , , and . DAC, page 59-65. ACM/IEEE, (1981)An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3., , , , , , , and . DAC, page 812-819. ACM/IEEE, (1981)A Fast Characterizing Method for Large Embedded Memory Modules on SoC., , , , , and . IEICE Transactions, 90-A (4): 815-822 (2007)A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays.. IEEE Trans. on CAD of Integrated Circuits and Systems, 4 (3): 329-336 (1985)Symbolic Layout System: Application Results and Functional Improvements., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (3): 346-354 (1987)A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint., , and . DAC, page 96-102. IEEE Computer Society Press, (1990)A consideration of the number of horizontal grids used in the routing of a masterslice layout., , , and . DAC, page 121-128. ACM/IEEE, (1982)Delayed-ABC SOI for crosstalk noise repair., , , , , , , and . IEICE Electronic Express, 5 (9): 354-360 (2008)