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Calculation of LFSR Seed and Polynomial Pair for BIST Applications.

, , and . DDECS, page 275-278. IEEE Computer Society, (2008)

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A suite of IEEE 1687 benchmark networks., , , , , , , , and . ITC, page 1-10. IEEE, (2016)New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams., , , and . DDECS, page 251-254. IEEE Computer Society, (2015)SoC and Board Modeling for Processor-Centric Board Testing., , , and . DSD, page 575-582. IEEE Computer Society, (2011)Automatic SoC Level Test Path Synthesis Based on Partial Functional Models., , , and . Asian Test Symposium, page 532-538. IEEE Computer Society, (2011)Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks., , , and . ETS, page 1-6. IEEE, (2019)Testing beyond the SoCs in a lego style., , and . EWDTS, page 334-338. IEEE Computer Society, (2010)On automatic software-based self-test program generation based on high-level decision diagrams., , and . LATS, page 177. IEEE, (2016)Laboratory framework TEAM for investigating the dependability issues of microprocessor systems., , , and . EWME, page 80-83. IEEE, (2014)FPGA-controlled PCBA power-on self-test using processor's debug features., , , , and . DDECS, page 125-130. IEEE, (2016)Calculation of LFSR Seed and Polynomial Pair for BIST Applications., , and . DDECS, page 275-278. IEEE Computer Society, (2008)