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Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits., , and . Scalable Computing: Practice and Experience, (2011)Asynchronous Fault Detection in IEEE P1687 Instrument Network., , and . NATW, page 73-78. IEEE, (2014)Collaborative Distributed Computing in the Field of Digital Electronics Testing., , and . BASYS, volume 322 of IFIP Advances in Information and Communication Technology, page 145-152. Springer, (2010)Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs., , , and . European Test Symposium, page 131-136. IEEE Computer Society, (2007)On coverage of timing related faults at board level., , and . ETS, page 1-2. IEEE, (2016)Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits., , , , and . DSD, page 658-663. IEEE Computer Society, (2010)Functional self-test of high-performance pipe-lined signal processing architectures., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 909-918 (2015)Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra., , , and . Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1130-1138 (2015)Effective Scalable IEEE 1687 Instrumentation Network for Fault Management., , and . IEEE Design & Test, 30 (5): 26-35 (2013)On in-system programming of non-volatile memories., , , and . MIXDES, page 408-413. IEEE, (2013)