PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Takeuchi, Ken"

Author of the publication

copydeleteadd this publication to your clipboard
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.

, , , and . IEEE Trans. on Circuits and Systems, 59-I (8): 1635-1643 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

PD Dr. Martin Kenner University of Stuttgart

Finn Kenklies University of Stuttgart

 

Other publications of authors with the same name

LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives., , , , and . IEEE Trans. VLSI Syst., 24 (1): 115-128 (2016)Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM., , , and . IEEE Trans. on Circuits and Systems, 59-I (8): 1635-1643 (2012)Design Considerations for an Information Query Computer., , , , , and . Advanced Database Machine Architecture, page 130-167. Prentice-Hall, (1983)Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression., , , , , and . ASP-DAC, page 81-82. IEEE, (2013)Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme., , and . ASP-DAC, page 83-84. IEEE, (2013)A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy., , , and . J. Solid-State Circuits, 48 (9): 2239-2249 (2013)An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories., , , , , , , and . J. Solid-State Circuits, 51 (4): 1041-1050 (2016)Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory., , , , , , , and . J. Solid-State Circuits, 51 (8): 1938-1951 (2016)0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications., , , , and . A-SSCC, page 1-4. IEEE, (2015)Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process., , , and . ESSCIRC, page 67-70. IEEE, (2016)