PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Liang, Huaguo"

Author of the publication

copydeleteadd this publication to your clipboard
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.

, , and . J. Electronic Testing, 17 (3-4): 341-349 (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Liang, Huaguo
add a person with the name Liang, Huaguo
 

Other publications of authors with the same name

Pulse shrinkage based pre-bond through silicon vias test in 3D IC., and . VTS, page 1-6. IEEE Computer Society, (2015)A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding., , , and . PRDC, page 11-16. IEEE Computer Society, (2009)Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST., , and . J. Electronic Testing, 18 (2): 159-170 (2002)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 755-766 (2019)A Dictionary-Based Test Data Compression Method Using Tri-State Coding., , , and . ATS, page 42-47. IEEE, (2018)A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE., , , , , and . ATS, page 121-126. IEEE, (2018)A Region-Based Through-Silicon via Repair Method for Clustered Faults., , , , , and . IEICE Transactions, 100-C (12): 1108-1117 (2017)Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs., , , , and . IEICE Electron. Express, 18 (2): 20200420 (2021)Test data compression scheme based on variable-to-fixed-plus-variable-length coding., , , and . Journal of Systems Architecture, 53 (11): 877-887 (2007)Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding., , , and . VLSI-DAT, page 1-4. IEEE, (2014)