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Built-in Self Repair by Reconfiguration of FPGAs., , and . IOLTS, page 187-188. IEEE Computer Society, (2006)Hardware/Software Based Hierarchical Self Test for SoCs., , , , , and . DDECS, page 159-160. IEEE Computer Society, (2006)Flip-Flops and Scan-Path Elements for Nanoelectronics., and . DDECS, page 307-312. IEEE Computer Society, (2007)A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features., , and . IOLTS, page 241-246. IEEE Computer Society, (2005)A Configurable Modular Test Processor and Scan Controller Architecture., , , , and . IOLTS, page 277-284. IEEE Computer Society, (2007)Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures., and . DSD, page 283-290. IEEE Computer Society, (2010)Embedded Self Repair by Transistor and Gate Level Reconfiguration., , , , and . DDECS, page 210-215. IEEE Computer Society, (2006)Embedded Scan Test with Diagnostic Features for Self-Testing SoCs., , , , , and . IOLTS, page 181-182. IEEE Computer Society, (2006)Logic Self Repair., , and . ARCS Workshops, volume P-81 of LNI, page 36-44. GI, (2006)A Scan Controller Concept for Low Power Scan Tests., and . J. Low Power Electronics, 4 (3): 420-428 (2008)